The Search for Semiconductor IP Intensifies

by Ron Wilson EE Times, 20 Jun 2005 Simple arithmetic can show the necessity for intellectual-property reuse in system-level chip design. A modest system-on-chip requires millions of gates. Each designer is capable of averaging perhaps a few tens of fully verified gates per day. Unless substantial portions of the chip are reused from previous designs or licensed from third parties, either the design team will grow to the Intel-esque scale or the schedule will span a geological time frame. Read the article