Concurrent Processing Memory

by Chengpu Wang & Zhen Wang arXiv.org E-print Archive, 15 Aug 2006 A novel memory with limited processing power and internal connectivity at each element is proposed. This memory carries out parallel processing within itself. Many common algorithms using this memory are discussed. For an array of N items, it reduces the total instruction cycle count of universal operations such as insertion and match finding to ~ 1, and local operations such as filtering and pattern recognition to ~ local operation size. It also reduces the global operations sum and sorting to ~√N and less than ~N instruction cycles respectively. Particularly, it eliminates most streaming activities for data processing purpose on the data bus. Yet it remains general-purposed, easy to use, pin compatible with conventional memory, and practical for implementation. Read more