Self-Assembled Templates Guide Growth of Nanostructures on a Silicon Substrate

by James Owen SPIE Newsroom, accessed 20 Jul 2006 To build next-generation nanoelectronic devices -- composed of switchable molecules, carbon nanotubes, and so on -- arranging and interconnecting the nanoscale components creates a significant challenge. The problem arises when trying to fabricate features just a few nanometers wide across an entire device. Conventional or top-down lithographic techniques are reaching their limits at 65nm. Direct-writing techniques, such as electron-beam and scanning-probe-microscope lithography, can theoretically write lines one-atom wide, but these techniques do not scale up to patterning across an entire substrate, such as silicon. To address these issues, many bottom-up techniques based upon the assembly of nanostructures are currently being developed. Read more