SEMATECH Identifies Top Technical Challenges for 2006; Adds Transistor Scaling

PhysOrg, 20 Apr 2005 SEMATECH today announced its Top Technical Challenges for 2006, continuing to underscore advanced gate stack, 193 nm immersion and EUV lithography, mask infrastructure, and low-k dielectrics with process compatibility. Consortium leaders also placed planar bulk transistor scaling on the list for the first time. Read the article